The present invention relates to a method of manufacturing a semiconductor device, as well as to a semiconductor device fabrication technique; and, more particularly, the invention relates to a technique which is effectively applicable to a method of manufacturing a semiconductor device which requires terminals, as well as the semiconductor device, or a method of manufacturing a semiconductor device which requires a reservoir in a hole for connection between different layers, as well as to the semiconductor device itself.
In a typical semiconductor device, for example, an upper-layer wiring line and a lower-layer wiring line are electrically connected to each other through a hole. First, the reason for the need for a reservoir will be described. For example, according to Japanese Unexamined Patent Publication No. Hei 9(1997)-266249, in a through hole for connection between a certain wiring layer and a wiring layer which overlies or underlies the said wiring layer, there occurs an electro-migration (EM) phenomenon, such that a direct current flows between the through hole and the wiring line, resulting in the flowing out of atoms which constitute the wiring line. In this case, there arises the problem that a void is formed eventually in the wiring line portion from which the atoms have flowed out, leading to a breaking of the wiring line. Or, even if such a breaking of the wiring line does not occur, an increase in the contact resistance between the through hole and the wiring line results, causing malfunction of the semiconductor device.
To avoid such an EM phenomenon, for example, according to the above-referred publication Hei 9(1997)-266249, a surplus portion, i.e., a reservoir, is provided at a wiring end, allowing it to serve as a supply source for replenishing the atoms that flow out, thereby prolonging the EM life of the wiring line. However, there is a concern that the provision of such a reservoir may result in a lowering of the integration density of the wiring. In this regard, for example, in Japanese Unexamined Patent Publication No. Hei 10(1998)-233442, it is described that, by thickening a metal accumulating portion of a wiring layer, it is possible to improve the EM resistance of the wiring layer without making the wiring length large. Further, for example, according to Japanese Unexamined Patent Publication No. 2001-44196, a metallic reservoir is provided near a wiring end and is connected mechanically to a lower or upper side of the wiring.
However, the present inventor has found that the above-described reservoir technique involves the following problem.
In the above-referenced literature, notice is taken of an intermediate portion of wiring, but it is at the beginning and end terminal portions of wiring that a bad influence of the reservoir appears more conspicuously. At each terminal portion it is necessary to ensure that the wiring is connected to a point of the terminal of concern. In this regard, if a reservoir cannot be formed at the wiring portion, the wiring may be completed bypasswise. That is, wiring may be bypassed in order to form a through hole at a position where a reservoir can be formed, whereas, in the case of a terminal, the wiring must be made to an absolute position of the terminal. Thus, the difficulty of wiring attributable to a reservoir at the terminal portion is enhanced. Particularly, an ordinary cell has plural terminals for input and output, and the occurrence of a reservoir at the terminal portion imposes a restriction on the arrangement of terminals near the terminal of concern.
The above-described problem will now be described by way of example with reference to FIGS. 30 to 34, which illustrate principal portions of selected planes in a layout design of wiring layers which constitute a semiconductor device. In FIGS. 30 to 34, there are arranged plural wiring channels Cx extending in the right and left directions and plural wiring channels Cy extending perpendicularly to the wiring channels Cx so as to form a lattice. The wiring channels Cx represent first layer wiring channels, while the wiring channels Cy represent second layer wiring channels, which overlie the first layer wiring channels.
First, FIG. 30 shows an example in which terminals 50a and 50b are arranged side by side on lattice points which are adjacent to each other in the right and left directions, as seen in FIG. 30. The terminals 50a and 50b are each formed as a square pattern including only one lattice point. Reservoirs 51a1˜51a4 and 51b1˜51b4 having the possibility of arrangement are disposed along the four sides of the terminals 50a and 50b, respectively. Usually, the spacing between wiring channels is set at a spacing which uses, as a basic unit, a distance corresponding to the sum of a minimum wiring width and a minimum wiring spacing, thereby ensuring as many available wiring channels as possible. Therefore, the reservoir 51a4 at the terminal 50a does not satisfy the minimum space to be left between it and the terminal 50b opposed thereto, and, thus, it becomes impossible to properly dispose the reservoir 51a4. It also becomes impossible to properly dispose the reservoir 51b2 at the terminal 50b. That is, as to the terminal 50a, only the reservoirs 51a1 and 51a3 can be provided, while, as to the terminal 50b, only the reservoirs 51b1 and 51b3 can be provided. As a result, it is only when a first wiring (the same layer as the terminals 50a and 50b), which overlies the upper and lower wiring channels Cx (Cxa, Cxb) shown in FIG. 30, is not present at lattice positions K1, K2, K3, and K4 lying on upper and lower sides of the terminals 50a and 50b that an upper-layer wiring can be connected to the terminals 50a and 50b. This is because, if the first wiring is present at the lattice positions K1, K2, K3, and K4, it becomes impossible to arrange the reservoirs 51a1, 51a3, 51b1, and 51b3. Thus, the capability of connection to the terminals 50a and 50b is limited to the case where the first wiring of the same layer as the terminals 50a and 50b is used for connection to both terminals, and the case where the first wiring is not present at the lattice positions K1, K2, K3, and K4.
Referring now to FIG. 31, an example is shown in which terminals 50a and 50b are arranged side by side on lattice points which are adjacent to each other in the vertical direction, as seen in FIG. 31. In this example, a reservoir 51a3 at the terminal 50a does not satisfy a minimum space to be left between it and the terminal 50b opposed thereto, and, therefore, it becomes impossible to provide the reservoir 51a3. It also becomes impossible to provide a reservoir 51b1 at the terminal 50b. That is, as to the terminal 50a in FIG. 31, only reservoirs 51a2 and 51a4 can be provided, while, as to the terminal 50b, only reservoirs 51b2 and 51b4 can be provided. As a result, it is only when a first wiring (the same layer as the terminals 50a and 50b), lying just under the wiring channels Cy (Cya, Cyb), is not present at lattice positions K5, K6, K7, and K8 lying on the left and right sides of the terminals 50a and 50b that an upper-layer wiring can be connected to the terminals 50a and 50b. That is, the capability of connection to the terminals 50a and 50b is limited to the case where the first wiring line is used for connection to the terminals 50a and 50b and the case where the first wiring is not present at the lattice positions K5, K6, K6, and K8. This is because, if the first wiring is present at the lattice positions K5, K6, K7, and K8, it becomes impossible to provide reservoirs 51a2, 51a4, 51b2, and 51b4, and, thus, even one reservoir cannot be disposed at the terminals 50a and 50b. For this reason it is only when the first wiring of the same layer as the terminals 50a and 50b is used for connection to both terminals and when the first wiring is not present at the lattice positions K5, K6, K7, and K8 that it becomes possible to make a connection to the terminals 50a and 50b. 
Further, FIG. 32 shows an example in which terminals 50a and 50b are arranged on lattice points which are adjacent to each other obliquely in the same figure. In this example, a reservoir 51b1 at the terminal 50b does not satisfy the minimum space requirement between it and a reservoir 51a4 at the terminal 50a opposed thereto, so that the concurrent occurrence of both reservoirs is impossible. It also becomes impossible for a reservoir 51b2 to be present concurrently with a reservoir 51a3. Thus, reservoirs which can occur at the terminal 50a are determined by a relation thereof to a reservoir which is present at the terminal 50b. When the reservoir 51b1 is present, only reservoirs 51a1 and 51a3 can be provided, while, when the reservoir 51b2 is present, only reservoirs 51a2 and 51a4 can be provided. Also, as to the terminal 50b, reservoirs which can be provided are determined by the relation thereof to a reservoir which is present at the terminal 50a. When the reservoir 51a is present, only reservoirs 51b1 and 51b3 can be provided, while, when the reservoir 51a4 is present, only reservoirs 51b2 and 51b4 can be provided. As a result, it is when there is no first wiring pattern at a lattice position K10 in the presence of the reservoir 51b1 or when there is no first wiring pattern at a lattice position K9 in the presence of the reservoir 51b2 that it is possible to make a connection from an upper-layer wiring to the terminal 50a. Likewise, it is when there is no first wiring pattern at the lattice position K10 in the presence of the reservoir 51a4, or when there is no first wiring pattern at the lattice position K9 in the presence of the reservoir 51a3, that it becomes possible to make a connection from an upper-layer wiring to the terminal 50b. That is, the capability of connection to the terminals 50a and 50b is limited to the case where the first wiring is used for connection and the case where there is no first wiring at the lattice positions K9 and K10. Thus, for connection to a terminal, it is necessary that a pattern of the same layer as the terminal not be present at a lattice position close to the terminal.
Next, with reference to FIG. 33, consideration will be given to the case where the terminal spacing is widened. FIG. 33 is a plan view showing a layout of terminals in a cell which the present inventor has studied. In figure there are plural terminals 50a and reservoirs 51a1˜51a4 having the possibility of arrangement for each of the terminals. The terminals 50a are arranged while leaving a spacing corresponding to one channel in each of the vertical and transverse directions. In such an arrangement, there is no longer a possibility that the inconvenience of connection from an upper-layer wiring becomes impossible due to such obstruction to the occurrence of reservoirs, as illustrated in FIGS. 30 to 32. However, there is only one lattice position where each terminal 50a is disposed, so that, when the wiring channel (the wiring channel of the second-layer wiring) located above the terminal 50a of concern is used by another wiring, it is required, for connection to the terminal 50a, that the connection be made once through the first-layer wiring. After all, it becomes necessary that the first-layer wiring not be present at the lattice position adjacent to the relevant terminal.
According to another proposal, a vacant lattice position for reservoir formation and a vacant lattice position for going through the first-layer wiring are provided at a lattice position adjacent to the relevant terminal beforehand as a reservation area. This method will now be described with reference to FIG. 34. A reservation area 52 corresponding to one channel is provided around each terminal 50a in such a manner that adjacent reservation areas do not overlap each other. In such an arrangement, the inconvenience of connection from an upper-layer wiring, due to an obstruction to the occurrence of reservoirs as illustrated in FIGS. 30 to 32, is eliminated, and the connectability can be improved because each reservation area 52 is applicable also as a vacant lattice position for going through the first-layer wiring. However, the adoption of such a construction results in the necessity of an extremely large extra area, so that in a cell having a particularly large number of terminals and fewer transistors, a relatively larger area is required, and, thus, the wasted area increases in size.